1. Field of the Invention
The present invention relates to a testing method and test apparatus arranged in a semiconductor apparatus in which a to-be-tested circuit such as a random access memory (RAM) arranged in the semiconductor apparatus is tested to guarantee a correctly-performed normal operation of the semiconductor apparatus on condition that a redundancy circuit of the to-be-tested circuit is controlled according to a self-repair function of the semiconductor apparatus so as to avoid the use of a faulty portion of the to-be-tested circuit.
2. Description of Related Art
FIG. 17 is a block diagram showing the configuration of a conventional test device arranged in an electronic system (or a semiconductor apparatus) having a self-repair function. In the conventional test device arranged in the electronic system, a random access memory (RAM) of the electronic system is self-repaired by using the conventional test device.
In FIG. 17, a reference sign 100 indicates an electronic system (corresponding to a semiconductor apparatus) operable at each of a normal operation mode and a self-repair operation mode, and a reference sign 1 indicates a RAM to be self-tested and self-repaired. The RAM 1 has redundancy memory cells, so that a data storing capacity of the RAM 1 is larger than that required to perform a desired normal operation of the electronic system 100. A reference sign 2 indicates a logical circuit. The RAM 1 and the logical circuit 2 are arranged to perform the desired normal operation of the electronic system 100.
A reference sign 3 indicates a redundancy control circuit (hereinafter referred to as either redundancy control circuit or redundant control circuit). The redundancy control circuit 3 controls a signal transmission between the RAM 1 and the logical circuit 2 not to use a faulty portion of the RAM 1 at the normal operation mode of the electronic system 100. Also, the redundancy control circuit 3 controls a signal transmission between the RAM 1 and a RAM built-in self test circuit described later at the self-repair operation mode of the electronic system 100.
A reference sign 4 indicates the RAM built-in self-test circuit described above, and the RAM built-in self-test circuit 4 generates a test pattern to test the RAM 1 in the self-repair operation, checks output data produced in the RAM 1 in response to the test pattern and outputs a test result indicating whether the RAM 1 is correctly operated. A reference sign 5 indicates a RAM built-in self-repair circuit arranged for the RAM 1. The RAM built-in self-repair circuit 5 controls the redundant control circuit 3 at each of the operation modes (the normal operation mode and the self-repair operation mode), controls the RAM built-in self-test circuit 4 at the self-repair operation mode, collects the test result from the RAM built-in self-test circuit 4 at the self-repair operation mode and judges according to the test result whether or not the repair of the RAM 1 is possible.
A reference sign 6 indicates a logic built-in self-test circuit arranged to test the logical circuit 2. The logic built-in self-test circuit 6 generates pseudo-random numbers to test the logical circuit 2 and compresses an output result produced in the logical circuit 2 in response to the pseudo-random numbers.
The test device arranged in the electronic system 100 (or the semiconductor apparatus) is composed of the logical circuit 2, the RAM built-in self-test circuit 4, the RAM built-in self-repair circuit 5 and the logic built-in self-test circuit 6.
To compress the test result in the RAM built-in self-test circuit 4, a signature register type compressing unit is generally used. Also, because the logic built-in self-test circuit 6 is not necessarily required to perform a self-repair operation for the RAM 1, there is a case that the logic built-in self-test circuit 6 is omitted.
Next, an operation of the conventional test device is described.
FIG. 18 is a flow chart showing the procedure of a self-repair operation performed by the conventional test device shown in FIG. 17.
In a self-repair operation, the RAM built-in self-repair circuit 5 controls the redundant control circuit 3 and the RAM built-in self-test circuit 4, a test pattern generated in the RAM built-in self-test circuit 4 is transmitted to the RAM 1, and a test of the RAM 1 is performed (step ST1). In detail, output data of the RAM 1 is obtained in the RAM built-in self-test circuit 4 through the redundant control circuit 3, and it is judged by the RAM built-in self-test circuit 4 according to the output data whether or not a faulty portion exists in the RAM 1.
In cases where a faulty portion exists in the RAM 1, the RAM built-in self-repair circuit 5 collects a test result from the RAM built-in self-test circuit 4, and it is judged by the RAM built-in self-repair circuit 5 according to the test result whether or not the repair of the faulty portion of the RAM 1 is possible (step ST2). In cases where the repair of the faulty portion of the RAM 1 is possible, the RAM built-in self-repair circuit 5 controls the redundant control circuit 3 not to use the faulty portion of the RAM 1 in a normal operation(step ST3). That is, the redundant control circuit 3 controls the RAM 1 to use its redundancy memory cells in place of the faulty portion in the normal operation.
The above-described test device arranged in the electronic system 100 (or the semiconductor apparatus) having a self-repair function is, for example, disclosed in the Published Unexamined Japanese Patent Application H8-94718 (1996). Also, as is described in the U.S. Pat. No. 5,956,350, a technique, in which a self-repair is performed to avoid the use of faulty locations under a system temperature-rise condition, is known.
However, because the RAM built-in self-repair circuit 5 controls the redundant control circuit 3 according to a result of one test performed for the RAM 1 in the conventional test device, in cases where a fault not detected under ordinary conditions (for example, ordinary power supply voltage and temperature) set in one test exists in the RAM 1, there is a problem that a control of the RAM built-in self-repair circuit 5 for the redundant control circuit 3 to avoid the use of a portion relating to the faulty of the RAM 1 in specific conditions differing from the ordinary conditions cannot be correctly performed.
For example, in cases where a self-test of the electronic system 100 for the RAM 1 is performed just after an electric power is supplied to the electronic system 100 set to a low temperature (or an ambient temperature), a specific fault of the RAM 1 occurring only in cases where the RAM 1 is heated up to a high temperature corresponding to a stationary temperature in a normal operation of the electronic system 100 cannot be detected. In cases where the specific fault exists in the RAM 1, the electronic system 100 malfunctions under the high temperature condition.
In contrast, as is described in the U.S. Pat. No. 5,956,350, in cases where a self-test of the electronic system 100 for the RAM 1 is performed under a high temperature condition, a fault of the RAM 1 occurring only in cases where the RAM 1 is set to a low temperature cannot be detected. In cases where this fault exists in the RAM 1, the electronic system 100 malfunctions under the low temperature condition. Because the electronic system 100 has a power save function, there is a case that the electronic system 100 is cooled to a low temperature even though the electric power is supplied to the electronic system 100. Also, in cases where the electronic system 100 is a portable device, the electronic system 100 is cooled to a low temperature when an ambient temperature is suddenly lowered. Therefore, there is a problem in cases where a self-test of the electronic system 100 for the RAM 1 is performed under a high temperature condition.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional test device for testing the semiconductor circuit, a testing method and test apparatus of a semiconductor apparatus in which a to-be-tested circuit arranged in the semiconductor circuit is tested, while considering a change of a test condition, to guarantee a correct working of the to-be-tested circuit after a self-repair of the to-be-tested circuit and to improve the reliability of the test of the to-be-tested circuit for the test condition change.
The object is achieved by the provision of a method of testing a to-be-tested circuit having a redundancy circuit, comprising, an initial test condition testing step of performing a logical test of the to-be-tested circuit under a first test condition to obtain first fault information and judging, according to the first fault information, whether or not the repair of the faulty portion of the to-be-tested circuit by the redundancy circuit is possible, and a confirmation step including a first step of performing a logical test, which is the same as the logical test performed in the initial test condition testing step, for the to-be-tested circuit under a second test condition different from the first test condition to obtain second fault information, in a case where it is judged that the repair of the faulty portion of the to-be-tested circuit is possible, and a second step of comparing the first fault information with the second fault information to obtain a comparison result which indicates whether the to-be-tested circuit is correctly operable under each of the first test condition and the second test condition.
In the above steps, the logical test is performed for the to-be-tested circuit at first under the first test condition, and the same logical test is performed for the to-be-tested circuit under the second test condition. In cases where the first fault information obtained from the logical test under the first test condition agrees with the second fault information obtained from the logical test under the second test condition, because a fault of the to-be-tested circuit occurring under the first test condition is the same as that occurring under the second test condition, in cases where a redundancy circuit of the to-be-tested circuit is controlled to avoid the use of the faulty portion of the to-be-tested circuit detected in the logical test under the first test condition, a correct operation of the to-be-tested circuit under each of the first test condition and the second test condition can be confirmed.
Accordingly, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the test condition, and the reliability of the test of the to-be-tested circuit for the test condition change can be improved in the testing method for the to-be-tested circuit arranged in the semiconductor apparatus.
It is preferred that the testing method further comprises a test condition change giving step of giving a change to the first test condition to change a test condition, under which the to-be-tested circuit is tested, to obtain the second test condition.
Because the first test condition is changed to the second test condition in the test condition change giving step, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the test condition, and the reliability of the test of the to-be-tested circuit for the test condition change can be improved in the testing method for the to-be-tested circuit.
It is also preferred that the test condition change giving step includes a step of performing a pseudo-logical test for the to-be-tested circuit or a circuit arranged in a periphery of the to-be-tested circuit to change the test condition.
Because the pseudo-logical test is performed for the to-be-tested circuit or the peripheral circuit to change the first test condition to the second condition, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the test condition, and the reliability of the test of the to-be-tested circuit for the test condition change can be improved in the testing method for the to-be-tested circuit arranged in the semiconductor apparatus.
It is also preferred that the test condition change giving step further includes a step of judging whether a test condition, under which the to-be-tested circuit is tested, reaches the second test condition, wherein the step of performing the pseudo-logical test is repeated in a case where it is judged in the judging step that the test condition does not reach the second test condition.
Therefore, the test for guaranteeing the correct operation of the to-be-tested circuit can be correctly performed while considering a time change of the test condition, and the reliability of the test of the to-be-tested circuit for the test condition change can be moreover improved in the testing method for the to-be-tested circuit.
It is also preferred that the first and second steps of the confirming step are repeated prescribed times with a change given to the second test condition, wherein the confirming step further includes a step of confirming a correct operation of the to-be-tested circuit according to a comparison result obtained every time the second step is performed.
Therefore, the correct operations of the to-be-tested circuit under the first test condition and the changing test conditions can be consecutively confirmed, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the test condition, and the reliability of the test of the to-be-tested circuit for the test condition change can be improved in the testing method for the to-be-tested circuit arranged in the semiconductor apparatus.
It is also preferred that the first and second steps of the confirming step are repeated until the second test condition reaches a predetermined test condition.
Therefore, the correct operation of the to-be-tested circuit can be consecutively confirmed in the test condition range from the first test condition to the changing test condition differing from the first test condition by the fixed value, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the test condition in the test condition range, and the reliability of the test of the to-be-tested circuit for the test condition change can be improved in the testing method for the to-be-tested circuit arranged in the semiconductor apparatus.
It is also preferred that the first test condition corresponds to a first temperature of the to-be-tested circuit, and the second test condition corresponds to a second temperature of the to-be-tested circuit.
Because the temperature of the to-be-tested circuit is adopted as the test condition, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the temperature of the to-be-tested circuit, and the reliability of the test of the to-be-tested circuit can be improved in the testing method for the to-be-tested circuit.
It is also preferred that the first test condition corresponds to a first power supply voltage applied to the to-be-tested circuit, and the second test condition corresponds to a second power supply voltage applied to the to-be-tested circuit.
Because the power supply voltage applied to the to-be-tested circuit is adopted as the test condition, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the power supply voltage applied to the to-be-tested circuit, and the reliability of the test of the to-be-tested circuit for the change of the power supply voltage applied to the to-be-tested circuit can be improved in the testing method for the to-be-tested circuit arranged in the semiconductor apparatus.
The object is also achieved by the provision of a test apparatus of a to-be-tested circuit, comprising a register for storing first fault information obtained by performing a logical test of the to-be-tested circuit under a first test condition, and a test circuit for judging according to the first fault information stored in the register whether or not a faulty portion exists in the to-be-tested circuit, judging according to the first fault information whether or not the repair of the faulty portion of the to-be-tested circuit is possible in a case where the faulty portion exists in the to-be-tested circuit, performing a logical test, which is the same as the logical test performed under the first test condition, for the to-be-tested circuit under a second test condition different from the first test condition to obtain second fault information in a case where the repair of the faulty portion of the to-be-tested circuit is possible, and comparing the first fault information with the second fault information to obtain a comparison result which indicates whether the to-be-tested circuit is correctly operable under each of the first test condition and the second test condition.
In the above configuration, in the test circuit, the existence of the faulty portion of the to-be-tested circuit is judged according to the first fault information obtained from the logical test of the to-be-tested circuit under the first test condition, and it is judged according to the first fault information that the repair of the faulty portion of the to-be-tested circuit is possible by avoiding the use of the faulty portion of the to-be-tested circuit. Thereafter, the logical test of the to-be-tested circuit under the second test condition is performed to obtain a second fault information, and the second fault information is compared with the first fault information. In cases where the second fault information agrees with the first fault information, because no faulty portion newly occurs under the second test condition other than the faulty portion of the to-be-tested circuit of which the repair is possible, it is confirmed that the to-be-tested circuit is correctly operable under each of the first test condition and the second test condition.
Accordingly, the test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the test condition, and the reliability of the test of the to-be-tested circuit for the test condition change can be improved.
It is preferred that the test circuit performs a pseudo-logical test for the to-be-tested circuit or a circuit arranged in a periphery of the to-be-tested circuit to give a change to the first test condition.
Because a heat is generated by operating the to-be-tested circuit or the periphery circuit in the pseudo-logical test, the first test condition can be changed to the second test condition.
It is also preferred that the test circuit continues the pseudo-logical test until a test condition, under which the to-be-tested circuit is tested, reaches the second test condition.
In the above configuration, a heat is generated by operating the to-be-tested circuit or the periphery circuit in the pseudo-logical test, the first test condition can be changed to the second test condition. Also, in cases where a test condition detecting unit such as a temperature sensor is used to detect the first and second test conditions, the change of the test condition can be correctly set to the fixed value.
Accordingly, the test for guaranteeing the correct operation of the to-be-tested circuit can be correctly performed while considering a time change of the test condition, and the reliability of the test of the to-be-tested circuit for the test condition change can be moreover improved.
It is also preferred that the test circuit repeatedly performs the logical test, which is the same as the logical test performed under the first test condition, prescribed times with a change given to the second test condition, and performs a comparison of the first fault information with the second fault information obtained every time the logical test is performed, and the test circuit confirms, according to a comparison result obtained every time the comparison is performed, that the to-be-tested circuit is correctly operable.
In the above configuration, the logical test is repeatedly performed under a changing test condition while giving a change to the first test condition. Therefore, the test results of the to-be-tested circuit can be consecutively confirmed while considering a time change of the test condition, and the correct working of the to-be-tested circuit can be guaranteed under the first test condition and the changing test conditions.
It is also preferred that the test circuit repeatedly performs the logical test until the second test condition reaches a predetermined test condition.
In the above configuration, in cases where a test condition detecting unit such as a temperature sensor is used to detect the test condition, the change of the test condition can be correctly set to the fixed value. Therefore, the logical test is repeatedly performed under a changing test condition until the change between the first test condition and the changing test condition of the logical test reaches a fixed value.
Accordingly, the test results of the to-be-tested circuit can be consecutively confirmed while considering a time change of the test condition in the test condition range of the fixed value starting from the first test condition, the correct working of the to-be-tested circuit can be guaranteed, and the reliability of the test of the to-be-tested circuit for the test condition change can be moreover improved.
It is also preferred that the first test condition corresponds to a first temperature of the to-be-tested circuit, and the second test condition corresponds to a second temperature of the to-be-tested circuit.
The test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the temperature of the to-be-tested circuit, and the reliability of the test of the to-be-tested circuit can be improved.
It is also preferred that the first test condition corresponds to a first power supply voltage applied to the to-be-tested circuit, and the second test condition corresponds to a second power supply voltage applied to the to-be-tested circuit.
The test for guaranteeing the correct operation of the to-be-tested circuit can be performed while considering a time change of the power supply voltage applied to the to-be-tested circuit, and the reliability of the test of the to-be-tested circuit for the change of the power supply voltage applied to the to-be-tested circuit can be improved.
It is also preferred that the first and second steps of the confirming step are performed again with a change given to the second test condition when the comparison result indicates a match, while the first or second step is not performed any more when the comparison result indicates a mismatch.
It is also preferred that the test circuit further performs the logical test again with a change given to the second test condition when the comparison result indicates a match, while not performing the logical test any more when the comparison result indicates a mismatch.